Thread-Level Speculation on a CMP Can Be Energy Efficient
ثبت نشده
چکیده
While Chip Multiprocessors (CMP) with Thread-Level Speculation (TLS) have become the subject of intense research, processor designers in industry have reservations about their practical implementation. An often cited complaint is that TLS is too energy-inefficient to compete against conventional superscalars. This paper challenges the commonly-held view that TLS is energy inefficient. We identify the main sources of dynamic energy consumption in TLS. We then present very simple energy-centric optimizations to a TLS CMP architecture that cut the energy cost of TLS by over 60% on average with minimal performance impact. This represents a 26.5% reduction of the total on-chip energy. The resulting TLS CMP with 3-issue cores speeds-up full SpecInt 2000 codes (not just loops) by 1.27 times on average, while holding the energy cost of TLS to only 25.4%. The TLS CMP is slightly faster than a 6-issue superscalar at the same frequency, while consuming only 85% of its total on-chip power for these very challenging applications.
منابع مشابه
Performance and power comparison of Thread Level Speculation in SMT and CMP architectures
As technology advances, microprocessors that support multiple threads of execution on a single chip are becoming increasingly common. Improving the performance of general purpose applications by extracting parallel threads is extremely difficult, due to the complex control flow and ambiguous data dependences that are inherent to these applications. Thread-Level Speculation (TLS) enables specula...
متن کاملA Chip-Multiprocessor Architecture with Speculative Multithreading
ÐMuch emphasis is now placed on chip-multiprocessor (CMP) architectures for exploiting thread-level parallelism in an application. In such architectures, speculation may be employed to execute applications that cannot be parallelized statically. In this paper, we present an efficient CMP architecture for speculative execution of sequential binaries without source recompilation. We present the s...
متن کاملA Flexible, Efficient Concurrent Garbage Collector for Speculative Thread Processors
Michael Chen and Kunle Olukotun Computer Systems Lab, Stanford University Abstract In this paper, we introduce a novel garbage collector for Java to be used for processors with speculative threads support like the Hydra chip multiprocessor (CMP). Thread speculation permits parallel execution of sections of sequential code with data dependencies enforced in the hardware, eliminating the need for...
متن کاملThe Stanford Hydra CMP
0272-1732/00/$10.00 2000 IEEE The Hydra chip multiprocessor (CMP) integrates four MIPS-based processors and their primary caches on a single chip together with a shared secondary cache. A standard CMP offers implementation and performance advantages compared to wide-issue superscalar designs. However, it must be programmed with a more complicated parallel programming model to obtain maximum p...
متن کامل